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LOW NOISE, HIGH LINEARITY PACKAGED PHEMT * PERFORMANCE (1850 MHz) 30 dBm Output Power (P1dB) 13 dB Small-Signal Gain (SSG) 1.3 dB Noise Figure 45 dBm Output IP3 45% Power-Added Efficiency Evaluation Boards Available Available in Lead Free Finish: FPD3000SOT89E
FPD3000SOT89
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DESCRIPTION AND APPLICATIONS The FPD3000SOT89 is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT). It utilizes a 0.25 x 3000 m Schottky barrier Gate, defined by highresolution stepper-based photolithography. The recessed and offset Gate structure minimizes parasitics to optimize performance, with an epitaxial structure designed for improved linearity over a range of bias conditions and input power levels. The FPD3000 is available in die form and in other packages. Typical applications include drivers or output stages in PCS/Cellular base station high-interceptpoint LNAs, WLL and WLAN systems, and other types of wireless infrastructure systems.
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ELECTRICAL SPECIFICATIONS AT 22C
Parameter Power at 1dB Gain Compression Small-Signal Gain Power-Added Efficiency Noise Figure Output Third-Order Intercept Point (from 15 to 5 dB below P1dB) Saturated Drain-Source Current Maximum Drain-Source Current Transconductance Gate-Source Leakage Current Pinch-Off Voltage Gate-Source Breakdown Voltage Gate-Drain Breakdown Voltage IDSS IMAX GM IGSO |VP| |VBDGS| |VBDGD| Symbol P1dB SSG PAE NF IP3 Test Conditions VDS = 5 V; IDS = 50% IDSS VDS = 5 V; IDS = 50% IDSS VDS = 5 V; IDS = 50% IDSS; POUT = P1dB VDS = 5 V; IDS = 50% IDSS VDS = 5 V; IDS = 25% IDSS VDS = 5V; IDS = 50% IDSS Matched for optimal power Matched for best IP3 VDS = 1.3 V; VGS = 0 V VDS = 1.3 V; VGS +1 V VDS = 1.3 V; VGS = 0 V VGS = -5 V VDS = 1.3 V; IDS = 3 mA IGS = 3 mA IGD = 3 mA 0.7 12 12 750 42 45 930 1.5 800 2 1.0 16 16
Revised: 01/05/05 Email: sales@filcsi.com
Min 29.5 11.5
Typ 30 13 45 1.3 0.9
Max
Units dBm dB % dB
RF SPECIFICATIONS MEASURED AT f = 1850 MHz USING CW SIGNAL
dBm
1100
mA A mS
20 1.3
A V V V
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http:// www.filtronic.co.uk/semis
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
FPD3000SOT89
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ABSOLUTE MAXIMUM RATINGS1
Parameter Drain-Source Voltage Gate-Source Voltage Drain-Source Current Gate Current RF Input Power
2
Symbol VDS VGS IDS IG PIN TCH TSTG PTOT Comp.
3
Test Conditions -3V < VGS < +0V 0V < VDS < +8V For VDS > 2V Forward or reverse current Under any acceptable bias state Under any acceptable bias state Non-Operating Storage See De-Rating Note below Under any bias conditions 2 or more Max. Limits
Min
Max 8 -3 IDSS 30 600 175
Units V V mA mA mW C C W dB %
Channel Operating Temperature Storage Temperature Total Power Dissipation Gain Compression Simultaneous Combination of Limits
1 3
-40
150 3.5 5 80
2 TAmbient = 22C unless otherwise noted Max. RF Input Limit must be further limited if input VSWR > 2.5:1 Users should avoid exceeding 80% of 2 or more Limits simultaneously
Notes: * Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device. * Total Power Dissipation defined as: PTOT (PDC + PIN) - POUT, where: PDC: DC Bias Power PIN: RF Input Power POUT: RF Output Power * Total Power Dissipation to be de-rated as follows above 22C: PTOT= 3.5W - (0.025W/C) x TPACK where TPACK = source tab lead temperature above 22C (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 65C source lead temperature: PTOT = 3.5W - (0.025 x (65 - 22)) = 2.43W
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HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model. Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263. APPLICATIONS NOTES & DESIGN DATA Applications Notes are available from your local Filtronic Sales Representative or directly from the factory. Complete design data, including S-parameters, noise data, and large-signal models are available on the Filtronic web site. Evaluation Boards available upon request.
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Phone: +1 408 850-5790 Fax: +1 408 850-5766
http:// www.filtronic.co.uk/semis
Revised: 01/05/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
FPD3000SOT89
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BIASING GUIDELINES Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger number of components compared to self-bias or dual-biased. Such circuits should include provisions to ensure that Gate bias is applied before Drain bias, otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for additional information. Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode devices such as the FPD3000SOT89. Self-biased circuits employ an RF-bypassed Source resistor to provide the negative Gate-Source bias voltage, and such circuits provide some temperature stabilization for the device. A nominal value for circuit development is 1.2 for a 50% of IDSS operating point. For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point. Note that pHEMTs, since they are "quasi- E/D mode" devices, exhibit Class AB traits when operated at 50% of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25% to 33% of IDSS range is suggested. Such Class AB operation will not degrade the IP3 performance.
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PACKAGE OUTLINE
(dimensions in mm)
All information and specifications subject to change without notice. Phone: +1 408 850-5790 Fax: +1 408 850-5766
http:// www.filtronic.co.uk/semis
Revised: 01/05/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT * TYPICAL TUNED RF PERFORMANCE
Power Transfer Characteristic
FPD3000SOT89
32.0 31.0 Pout (dBm) 30.0 Output Power (dBm) 29.0 28.0 Comp Point
3.25 2.75 2.25 1.75 1.25 Gain Compression, (dB) Drain Efficiency (%)
27.0 26.0 25.0 24.0 23.0 11.0 0.75 0.25 -0.25 -0.75 23.0
13.0
15.0
17.0 Input Power (dBm)
19.0
21.0
Drain Efficiency and PAE
45% 40% 35% 30% PAE (%) 25% 20% PAE 15% 10% 5% 0% 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 21.0 22.0 Input Power (dBm) Eff. 15% 10% 5% 0% 45% 40% 35% 30% 25% 20%
Typical power and efficiency is shown above. The devices were biased nominally at VDS = 5V, IDS = 50% of IDSS, at a test frequency of 1.85 GHz. The test devices were tuned (input and output tuning) for maximum output power at 1dB gain compression.
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http:// www.filtronic.co.uk/semis
Revised: 01/05/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
FPD3000SOT89
Typical Intermodulation performance VDS = 5V, IDS = 50% IDSS at f = 1.85GHz -40.00 21
Pout (dBm) 3rds (dBc)
-42.00 -44.00 -46.00 -48.00 3rd Order IM Products (dBc)
19 Output Power (dBm)
17 -50.00 15 -52.00 -54.00 13 -56.00 -58.00 11 0.7 1.7 2.8 3.8 4.7 5.7 6.8 7.8 8.8 9.8
Inout Power (dBm)
-60.00
Note: pHEMT devices exhibit non-classical intermodulation performance, with equivalent IP3 values exceeding 14 dB above P1dB. This IMD enhancement is affected by the quiescent bias current, the Drain-Source voltage, and the tuning or matching applied to the device. Maximum Stable Gain & S21
35 30
FPD3000SOT89 5V / 50%IDSS
MSG S21
MSG Mag S21 &
25 20 15 10 5 0 0.5 1.5 2.5 3.5 4.5 5.5 Frequency (GHz) 6.5 7.5 8
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http:// www.filtronic.co.uk/semis
Revised: 01/05/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT * TYPICAL OUTPUT PLANE POWER CONTOURS (VDS = 5V, IDS = 50% IDSS)
FPD3000SOT89
0. 6 0.
0. 8
1. 0 2. 0
Swp Max 143
3.
0.
24dBm 25dBm 26dBm
0. 2
4. 5. 10. 0. 1. 8 0 2. 0 3. 4. 5. 0 00 10 .0
27dBm
0. 4 28dBm
0
0. 6
29dBm
-
30dBm
0. 2. 0. 1. -
1850 MHz Contours swept with a constant input power, set so that nominal P1dB is achieved at the point of optimum output match. Input (Source plane) s: 0.70 -165.5 0.17 - j0.12 (normalized) 8.5 - j6.0 Nominal IP3 performance is obtained with this input plane match, and the output plane match as shown.
Swp Min 1
0. 6 0.4
0. 8
1. 0 2. 0
Swp Max 131
3.0
0.2
24dBm 25dBm 26dBm 27dBm 28dBm
0. 0. 229dBm 4 0. 6 0. 8 1. 0 2. 0 3. 4. 5. 0 00
4.0 5.0
10.0 10 .0
0
30dBm
-0.2
-10.0
-5.0 -4.0 -0.4 2. 0 1. 0 -3.0
900 MHz Contours swept with a constant input power, set so that nominal P1dB is achieved at the point of optimum output match. Input (Source plane) s: 0.78 -147.4 0.13 - j0.29 (normalized) 6.5 - j14.5 Nominal IP3 performance is obtained with this input plane match, and the output plane match as shown.
0. 6
0. 8
Swp Min 1
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http:// www.filtronic.co.uk/semis
Revised: 01/05/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
*
FPD3000SOT89
TYPICAL SCATTERING PARAMETERS (50 SYSTEM)
See Website "More Info" for S-parameter design files.
FPD3000SOT89 5V / 50%IDSS
0. 6 0. 8
5 GHz
6 GHz
1. 0
7 GHz
Swp Max 8GHz
2. 0 3.0 4.0 5.0
4 GHz 0.4 3.5 GHz 3 GHz
0.2 2.5 GHz
2 GHz 1.5 GHz 1 GHz
-0.2 0 0. 2 0. 4 0. 6 0. 8 1. 0 2. 0 3. 0 4. 5. 00
10.0 10 .0
-10.0
-5.0 -4.0 -3.0 2. 0 1. 0
-0.4 0. 6
S11
0. 8
Swp Min 0.5GHz
FPD3000SOT89 5V / 50%IDSS
6 0.
Swp Max 8GHz
2. 0
0.8
5 GHz 4 GHz 3 GHz
6 GHz
1.0
0.2
0.4
0.6
0.8
1.0
2.0
3.0
4.0
5.0
0
1 GHz
10.0
.4 -0
-0.8
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http:// www.filtronic.co.uk/semis
-1.0
S22
-0 .6
-2
.0
Swp Min 0.5GHz
-5.
-4 .0
0
-0.
2
-10.0
-3 .
0
0. 4
7 GHz
3.
0
0 4.
5.0
0.2
2 GHz
10.0
Revised: 01/05/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
*
FPD3000SOT89
TYPICAL I-V CHARACTERISTICS
DC IV Curves FPD3000SOT89
1.2
1.0
Drain-Source Voltage (A)
0.8
0.6
0.4
VG=-1.50V VG=-1.25V VG=-1.00V VG=-0.75V VG=-0.50V VG=-0.25V VG=0V
0.2
0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Drain-Source Voltage (V)
Note: The recommended method for measuring IDSS, or any particular IDS, is to set the Drain-Source voltage (VDS) at 1.3V. This measurement point avoids the onset of spurious self-oscillation which would normally distort the current measurement (this effect has been filtered from the I-V curves presented above). Setting the VDS > 1.3V will generally cause errors in the current measurements, even in stabilized circuits. Recommendation: Traditionally a device's IDSS rating (IDS at VGS = 0V) was used as a predictor of RF power, and for MESFETs there is a correlation between IDSS and P1dB (power at 1dB gain compression). For pHEMTs it can be shown that there is no meaningful statistical correlation between IDSS and P1dB; specifically a linear regression analysis shows r2 < 0.7, and the regression fails the F-statistic test. IDSS is sometimes useful as a guide to circuit tuning, since the S22 does vary with the quiescent operating point IDS.
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http:// www.filtronic.co.uk/semis
Revised: 01/05/05 Email: sales@filcsi.com

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